Research
Research method¶
The method in use for get findings about the bitstream is simple: it's a iteration of different Verilog modules using Quartus Primer and checking for binary differences.
So the basis of the research is a iteration of:
- Generate a bitstream from Quartus
- Generate a second bitstream sightly different
- Do a binary comparison
- Try to understand the differences
I've created a Jupyter notebook which is very useful to analyze and visualize.
Generating bitstreams¶
In order to generate a files easier, I'm using this script to loop all the pins availables:
#!/bin/bash
export QUARTUS_PATH="/home/fran/intelFPGA_lite/24.1std/quartus/linux64"
export PART="EP4CE6E22C8"
export LD_LIBRARY_PATH=$QUARTUS_PATH:$LD_LIBRARY_PATH
export NAME="test"
#rm pins_*.rbf
rm simple.qsf
cp simple-start.qsf simple.qsf
$QUARTUS_PATH/quartus_map --part=$PART simple.v
INPUT=1
PREFIX=fixed1
for i in $(seq 2 144); do
cp simple-start.qsf simple.qsf
echo "set_location_assignment PIN_$i -to led1" >> simple.qsf
echo "set_location_assignment PIN_$INPUT -to key1" >> simple.qsf
$QUARTUS_PATH/quartus_fit --read_settings_files=on simple
if [ $? -ne 0 ]; then
echo "Fitting failed for PIN_$i"
continue
fi
$QUARTUS_PATH/quartus_asm --read_settings_files=on simple
if [ $? -ne 0 ]; then
echo "Assembly failed for PIN_$i"
exit 1
fi
$QUARTUS_PATH/quartus_sta simple
if [ $? -ne 0 ]; then
echo "Timing analysis failed for PIN_$i"
exit 1
fi
$QUARTUS_PATH/quartus_cpf -c output_files/simple.sof ${PREFIX}_${INPUT}_$i.rbf
echo "Writing to " ${PREFIX}_${INPUT}_$i.rbf
#cp output_files/simple.rbf ${PREFIX}_${INPUT}_$i.rbf
done
Depending of the topic I want to analyze I use different verilog code.
Analysis techniques¶
Mostly, the analysis is just parsing the sections and checking if they are equal, just that. In the case of core sections I'm reporting also the changes inside each section.
To visualize and find patters easier, I'm printing tables and a heatmap.