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Introduction

This projects aims to reverse engineer the Altera/Intel Cyclone IV FPGA family bitstream and provide a FOSS toolchain in combination with other existing tools like Yosys and NextPNR.

The project is in a very early stage. The initial situation is:

  • Yosys has some support for Verilog-to-Routing
  • NextPNR has no support for Cyclone IV
  • There is already a project for Cyclone V
  • OpenFPGALoader can flash .rfb files

Roadmap

The main effort now goes to understand the bitstream structure and be able to generate a new one from scratch as the first step into a reliable full toolchain. So the roadmap is:

  1. Analyze the bitstream structure
  2. Understand basics about I/O Pins, logic elements and routing
  3. Define FPGA constrains and integrate with the higher level tools
  4. Get a deeper understanding of all the elements of the FPGA

At the moment it's in the first stage, just at the beginning.

All the reserach is made over a EP4CE6E22C8, also over a EasyFPGA a2.2 board.

How to contribute

You can help to this project in many ways, feel free to share your knowledge about Cyclone IV, help implementing or simply star the repository.

In the case you want to push the research, I sugguest to look in the lastest updates for the most recent tasks. Feel free to contact me or anything for any help.

As this is a personal free-time project, any donation is highly appreciated and it will be used to buy hardware to test the project.

Contributors